Digital communication receivers typically sample an incoming waveform and then detect the sampled data. Typically, a receiver includes a Clock and Data Recovery (CDR) system to recover the clock and data from an incoming data stream. The CDR system generates a clock signal having the same frequency and phase as the incoming signal, which is then used to sample the received signal and detect the transmitted data.
U.S. patent application Ser. No. 10/965,138, filed Oct. 14, 2004, entitled “Parallel Sampled Multi Stage Decimated Digital Loop Filter for Clock/Data Recovery,” incorporated by reference herein, discloses a CDR architecture that uses an oversampled phase detector followed by a parallel sampled multi-stage decimated digital loop filter. The use of parallel sampled multi-stage decimated loop filtering significantly reduces the area and power required by previous analog loop filter based solutions. In addition, the circuit behavior of the digital loop filter can be verified against the architectural level behavior and the digital loop filter parameters are not subject to analog errors and process/voltage/temperature (PVT) variations. However, an implementation of the architecture makes use of an analog phase selection circuit (PSC) that is implemented as a voltage controlled delay line (VCDL). VCDL errors, however, can degrade good jitter tolerance performance.
It is therefore desirable to further reduce the proportion of analog circuitry determining the performance of the CDR loop. Digital interpolation has been used to perform an all digital timing recovery that eliminates most analog errors and PVT variations. See, for example, F. Gardner, “Interpolation in Digital Modems—Part I: Fundamentals,” IEEE Trans. on Communications, 501-507 (March, 1993); L. Erup et al., “Interpolation in Digital Modems—Part II: Implementation and Performance,” IEEE Trans. on Communications, 998-1007 (June, 1993); M. Spurbeck and R. Behrens, “Interpolated Timing Recovery for Hard Disk Drive Read Channels,” Proc. IEEE Int'l Conf. on Communications (ICC), 1618-1624 (1997); or Z. Wu and J. Cioff, “A MMSE Interpolated Timing Recovery Scheme for the Magnetic Recording Channel,” IEEE Int'l Conf. on Communications (ICC) (1997). In such interpolated timing recovery (ITR) or interpolated clock/data recovery (ICDR) approaches, the interpolation filters and CDR loop filter process data at the full baud rate.
A need exists for methods and apparatus for digital ICDR that perform the timing recovery computations at less than the baud rate.